LENZE EVS9324-EK EVS9324-EK EVS9324-EK EVS9324-EK EVS9324-EK EVS9324-EK

You enable a parameter by setting the corresponding bit to "1".
The parameters for the 16 digital output channels are located in data records 64 to 79 and
are assigned as follows:
● Data record 64 for channel 0
● Data record 65 for channel 1
● …
● Data record 78 for channel 14
● Data record 79 for channel 15
Data record structure
The figure below shows the structure of data record 64 for channel 0 as an example. The
structure is identical for channels 1 to 15. The values in byte 0 and byte 1 are fixed and must
not be changed.
You enable a parameter by setting the corresponding bit to "1".You can change the parameters of the High Speed Counter in RUN. The WRREC instruction
is used to transfer the parameters to the High Speed Counter using data record 128.
If errors occur when transferring or validating parameters with the WRREC instruction, the
High Speed Counter continues operation with the previous parameter assignment. The
STATUS output parameter then contains a corresponding error code. If no error has
occurred, the length of the data actually transferred is entered in the STATUS output
parameter.
You will find a descrtion of the "WRREC" instruction and the error codes in the STEP 7
(TIA Portal) online help.
Data record structure
The following table shows you the structure of data record 128 with the counter channel. The
values in byte 0 to byte 3 are fixed and must not be changed. The value in byte 4 may only
be changed by parameter reassignment and not in RUN mode.Reserved bits must be set to 0
2) Must be set to 1 for the activation of the diagnostic interrupts "Missing supply voltage L+, "Illegal A/B signal ratio" and
"Hardware interrupt lost"0001B:
Counting: Between comparison value 0 and high counting
limit;
Measuring: Measured value >= Comparison value 0
0010B:
Counting: Between comparison value 1 and low counting
limit; Measuring: Measured value <= Comparison
value 1
0010B:
Counting: Between comparison value 0 and low counting
limit; Measuring: Measured value <= Comparison
value 0
0011B:
Counting: At comparison value 1 for one pulse duration;

Measuring: Reserved
0011B:
Counting: At comparison value 0 for one pulse duration;
Measuring: Reserved
0100B: Between comparison value 0 and 1 0100B: Reserved
0101B:
Counting: After set command from CPU until comparison
value 1;
Measuring: Reserved
0101B:
Counting: After set command from CPU until comparison
value 0;
Measuring: Reserved
0110B:
Counting: Reserved
Measuring: Not between comparison value 0 and 1

0110 to 1111B: Reserved
Response to gate start: Response to counting limit violation: Reset at counting limit violation:
00B: Set to start value 000B: Stop counting 000B: To other counting limit
01B: Continue with current
value
001B: Continue counting 001B: On start value
10 to 11B: Reserved 010 to 111B: Reserved 010 to 111B: ReserveAll other values: Reserved
The value range also applies for the 'Selection HSC DI1' parameter in
Selection HSC DI1
Value range:
The value range also applies for the 'Selection HSC DI0' parameter in
the same way.
0B: Not
used
1B: Used
51 Use of
HSC DQ1
Reserved = 0 1) Selection HSC DQYou have the option of reassigning the pulse width modulation parameters in RUN. The
parameters are transferred with the instruction WRREC via the data record 128 to the PWM
submodule.
If errors occur when transferring or validating parameters with the WRREC instruction, the
module continues operation with the previous parameter assignment. The output parameter
STATUS then contains a corresponding error code. If no error has occurred, the length of
the data actually transferred is entered in the output parameter STATUS.
You can find a descrtion of the "WRREC" instruction and the error codes in the STEP 7
(TIA Portal) online helpThe following table shows the structure of the data record 128 for the pulse width
modulation. The values in byte 0 to byte 3 are fixed and must not be changed.
An integrated analog-to-digital converter converts the analog signal into a digital signal so
that the compact CPU can process the analog signal read in by an analog channel. Once the
CPU has processed the digital signal, an integrated digital-to-analog converter converts the
output signal into an analog current or voltage value.The interference frequency suppression of the analog inputs suppresses the interference
caused by the frequency of the AC voltage network used. The frequency of the AC voltage
network may interfere with measured values, particularly for measurements within narrow
voltage ranges.
You set the line frequency with which the plant operates (400, 60, 50 or 10 Hz) using the
"Interference frequency suppression" parameter in STEP 7 (TIA Portal). The "Interference
frequency suppression" parameter can only be set module-wide (for all input channels). The
interference frequency suppression filters out the set interference frequency
(400/60/50/10 Hz) as well as multles of it. The selected interference frequency suppression
also defines the integration time. The conversion time changes depending on the set
interference frequency suppression.
For example, an interference frequency suppression of 50 Hz corresponds to an integration
time of 20 ms. The analog on-board I/O supplies one measured value to the CPU every
millisecond over a period of 20 ms. This measured value corresponds to the floating mean
value of the last 20 measurements.The following figure shows how this works using a 400 Hz interference frequency
suppression as an example. A 400 Hz interference frequency suppression corresponds to an
integration time of 2.5 ms. The analog on-board I/O supplies a measured value to the CPU
every 1.25 milliseconds within the integration time.The following figure shows how this works using a 60 Hz interference frequency suppression
as an example. A 60 Hz interference frequency suppression corresponds to an integration
time of 16.6 ms. The analog on-board I/O supplies a measured value to the CPU every 1.04
milliseconds within the integration time.The following figure shows how this works using a 50 Hz interference frequency suppression
as an example. A 50 Hz interference frequency suppression corresponds to an integration
time of 20 ms. The analog on-board I/O supplies a measured value to the CPU every
millisecond within the integration time.vWith an integration time of 2.5 ms, the measured value is changed by the following values