Place of Origin: | GERMANY |
Brand Name: | LENZE |
Certification: | CE |
Model Number: | EVS9329-ETV100 |
Minimum Order Quantity: | 1pcs |
---|---|
Packaging Details: | carton |
Delivery Time: | in stock |
Payment Terms: | T/T, Western Union, MoneyGram |
Supply Ability: | 100pcs/week |
LENZE: | LENZE | EVS9329-ETV100: | EVS9329-ETV100 |
---|---|---|---|
GERMANY: | GERMANY | Material: | Iron |
Dimension: | 80mm | Color: | Black |
Temperature: | 20-90 |
Data record 65 for channel 1 | |
Data record 78 for channel 14 ● Data record 79 for channel 15 |
|
Second submodule (X12): ● Data record 64 for channel 0 ● Data record 65 for channel 1 |
● Data record 78 for channel 14
● Data record 79 for channel 15The example in the figure below shows the structure of data record 64 for channel 0. The
structure is identical for channels 1 to 31. The values in byte 0 and byte 1 are fixed and must
not be changed.
You enable a parameter by setting the corresponding bit to "1".You can change the parameters of the High Speed Counter in RUN mode. The WRREC
instruction is used to transfer the parameters to the High Speed Counter using data
record 128.
If errors occur when transferring or validating parameters with the WRREC instruction, the
High Speed Counter continues operation with the previous parameter assignment. The
STATUS output parameter then contains a corresponding error code. If no error has
occurred, the length of ?the data actually transferred is entered in the STATUS? output
parameter.
You will find a description of the "WRREC" instruction and the error codes in the STEP 7
(TIA Portal) online help.
Data record structure
The following table shows you the structure of data record 128 with the counter channel. The
values in byte 0 to byte 3 are fixed and must not be changed. The value in byte 4 may only
be changed by parameter reassignment and not in RUN modeSignal evaluation: Signal type:
00B: Single 0000B: Pulse (A)
01B: Double 0001B: Pulse (A) and direction (B)
10B: Quadruple 0010B: Count up (A), count down (B)
11B: Reserved 0011B: Incremental encoder (A, B phase-shifted)
0100B: Incremental encoder (A, B, N)
0101 to 1111B: Reserved
7 Reaction to signal N: Invert direction
Reserved =
0 1)
Filter frequency
00B: No reaction to signal
N
0000B: 100 Hz
0001B: 200 Hz
01B: Synchronization at
signal N
0010B: 500 Hz
0011B: 1 kHz
10B: Capture at signal N 0100B: 2 kHz
11B: Reserved 0101B: 5 kHz
0110B: 10 kHz
0111B: 20 kHz
1000B: 50 kHz
1001B: 100 kHz
1010B: Reserved
1011 to 1111B: ReservedSet output (DQ1): Set output (DQ0):
0000B: Use by user program 0000B: Use by user program
0001B:
Counting: Between comparison value 1 and high limit;
Measuring: Measured value >= Comparison value 1
0001B:
Counting: Between comparison value 0 and high limit;
Measuring: Measured value >= Comparison value 0
0010B:
Counting: Between comparison value 1 and low limit;
Measuring: Measured value <= Comparison value 1
0010B:
Counting: Between comparison value 0 and low limit;
Measuring: Measured value <= Comparison value 0
0011B:
Counting: At comparison value 1 for one pulse duration;
Measuring: Reserved
0011B:
Counting: At comparison value 0 for one pulse duration;
Measuring: Reserved
0100B: Between comparison value 0 and 1 0100B: Reserved
0101B:
Counting: After set command from CPU until comparison
value 1;
Measuring: Reserved
0101B:
Counting: After set command from CPU until comparison
value 0;
Measuring: Reserved
0110B:
Counting: Reserved
Measuring: Not between comparison value 0 and 1
0110 to 1111B: ReservedBehavior of
count value
after Capture
(DI0):
Edge selection (DI0): Level selection
(DI0):
Reserved =
0 1)
Set function of the DI (DI0):
00B: Reserved 000B: Gate start/stop (level-triggered)
01B: On a rising edge 0B: Active at
high level
001B: Gate start (edge-triggered)
10B: On a falling edge 010B: Gate stop (edge-triggered)
0B: Continue
counting
11B: On rising and falling
edge
1B: Active at
low level
011B: Synchronization
100B: Enable synchronization at signal N
1B: Set to
start value
and continue
counting