TAMAGAWA TS5208N68 TS5208N68 TS5208N68 TS5208N68 TS5208N68 TS5208N68 TS5208N68

TS5208N68

Guang Zhou Lai Jie Electric Co.,LTD

Please contact with “Tommy” for the price

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PULSE

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750PPR

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M-52004

RP872ZL

Overshoot range (data word) 27,649 to 32,511
Overflow range 11.760 to 11.852 V
Overflow range (data word) 32,512 to 32,767
Resolution 10 bits
Maximum withstand voltage 35 VDC
Smoothing None, Weak, Medium, or Strong
See the table for step response (ms) for the analog inputs of the CPU
(Page 730).
Noise rejection 10, 50, or 60 Hz
Impedance ≥100 KΩ
Isolation (field side to logic) None
Accuracy (25°C / -20 to 60°C) 3.0% / 3.5% of full-scale
Cable length (meters) 100 m, shielded twisted p24 VDC Sensor Power
Out
For additional noise
immunity, connect "M"
to chassis ground even
if not using sensor
supply.
② For sinking inputs,
connect "-" to "M"
(shown).
For sourcing inputs,
connect "+" to "M".
 
X10
X11
X12
Note: X11 connectors must
be gold. See Appendix C,
Spare Parts for order
number. ① 24 VDC Sensor Power
Out
For additional noise
immunity, connect "M"
to chassis ground even
if not using sensor
supply.
② For sinking inputs,
connect "-" to "M"
(shown).
For sourcing inputs,
connect "+" to "M".
 
X11
X12
X10
Note: X11 connectors must
be gold. See Appendix C,
Spare Parts for order
numbe6ES7 215-1BG31-0XB0 6ES7 215-1HG31-0XB0 6ES7 215-1AG31-0XB0
Dimensions W x H x D (mm) 130 x 100 x 75 130 x 100 x 75 130 x 100 x 75
Shipping weight 550 grams 585 grams 520 grams
Power dissipation 14 W 12 W 12 W
Current available (SM and CM bus) 1600 mA max.
(5 VDC)
1600 mA max.
(5 VDC)
1600 mA max.
(5 VDC)
Current available (24 VDC) 400 mA max.
(sensor power)
400 mA max.
(sensor power)
400 mA max.
(sensor power)
Digital input current consumption
(24VDC)
4 mA/input used 4 mA/input used 4 mA/input used16 Kbytes for startup and program cycle (including associated FBs and FCs)
 4 Kbytes for standard interrupt events including FBs and FCs
 4 Kbytes for error interrupt events including FBs and FCs
Signal modules expansion 8 SMs max.

SB, CB, BB expansion 1 max.
Communication module expansion 3 CMs max.
High-speed counters 6 total, see table HSC input assignments for CPU 1215C
 Single phase: 3 at 100 kHz and 3 at 30 kHz clock rate
 Quadrature phase: 3 at 80 kHz and 3 at 20 kHz clock rate
Pulse outputs 2 4
Pulse catch inputs 14
Time delay / cyclic interrupts 4 total with 1 ms resolution
Edge interrupts 12 rising and 12 falling (14 and 14 with optional signal board)
Memory card SIMATIC Memory Card (optional)
Real time clock accuracy +/- 60 seconds/month
Real time clock retention time 20 days typ./12 days min. at 40°C (maintenance-free Super Capacitor) 1 The size of the user program, data, and configuration is limited by the available load memory and work memory in the
CPU. There is no specific limit to the number of OB, FC, FB and DB blocks supported or to the size of a particular block;
the only limit is due to overall memory size.
2 For CPU models with relay outputs, you must install a digital signal board (SB) to use the pulse outputs. Type OB, FB, FC, DB
Size 64 Kbytes
Quantity Up to 1024 blocks total (OBs + FBs + FCs + DBs)
Address range for FBs, FCs,
and DBs
1 to 65535 (such as FB 1 to FB 65535)
Blocks
Nesting depth 16 from the program cycle or start up OB; 4 from the time delay
interrupt, time-of-day interrupt, cyclic interrupt, hardwaMonitoring Status of 2 code blocks can be monitored simultaneously
Program cycle Multiple: OB 1, OB 200 to OB 65535
Startup Multiple: OB 100, OB 200 to OB 65535
Time-delay interrupts and
cyclic interrupts
41 (1 per event): OB 200 to OB 65535
Hardware interrupts (edges
and HSC)
50 (1 per event): OB 200 to OB 65535
Time error interrupts 1: OB 80
OBs
Diagnostic error interrupts 1: OB 82
Type IEC
Quantity Limited only by memory size
Timers
Storage Structure in DB, 16 bytes per timer
Type IEC
Quantity Limited only by memory size
Counters
Storage Structure in DB, size dependent upon count type
 SInt, USInt: 3 bytes
 Int, UInt: 6 bytes
 DInt, UDInt: 12 bytes
1 Time-delay and cyclic interrupts use the same resources in the CPU. You can have only a total of 4 of these interrupts
(time-delay plus cyclic interrupts). You cannot have 4 time-delay interrupts and 4 cyclic interrupts.
Table A- 66 Communication
Technical data Description
Number of ports 2
Type Ethernet
HMI device1 3
Programming device (PG) 1
Connections  8 for Open User Communication (active or passive): TSEND_C,
TRCV_C, TCON, TDISCON, TSEND, and TRCV
 3 for server GET/PUT (CPU-to-CPU) S7 communication The CPU provides dedicated HMI connections to support up to 3 HMI devices. (You can have up to 2 SIMATIC Comfort
panels.) The total number of HMI is affected by the types of HMI panels in your configuration. For example, you could
have up to three SIMATIC Basic panels connected to your CPU, or you could have up to two SIMATIC Comfort panels
with one additional Basic panel. Isolation (field side to logic) 500 VAC for 1 minute
Isolation groups 1
Filter times 0.2, 0.4, 0.8, 1.6, 3.2, 6.4, and 12.8 ms (selectable in groups of 4)
HSC clock input rates (max.)
(Logic 1 Level = 15 to 26 VDC)