 |
| Place of Origin: | Japan |
| Brand Name: | Tamagawa |
| Certification: | CE |
| Model Number: | TS5210N450 |
| Minimum Order Quantity: | 1pcs |
|---|---|
| Packaging Details: | carton |
| Delivery Time: | in stock |
| Payment Terms: | T/T, Western Union, MoneyGram |
| Supply Ability: | 100pcs/week |
| TAMAGAWA: | TAMAGAWA | Material: | Iron |
|---|---|---|---|
| Color: | Black | Japan: | Japan |
| TS5210N450: | TS5210N450 | Wire: | Wire |
| Temperature: | 20-90 | Dimension: | 70mm |
TS5210N450
Guang Zhou Lai Jie Electric Co.,LTD
Please contact with “Tommy” for the price
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| Signal modules expansion 8 SMs max. | High-speed counters 6 total, see table Operation of the high-speed counter (Page 339) |
| SB, CB, BB expansion 1 max. | Single phase: 3 at 100 kHz and 3 at 30 kHz clock rate, |
| Communication module expansion 3 CMs max. | Quadrature phase: 3 at 80 kHz and 3 at 20 kHz clock ra The size of the user program, data, |
and configuration is limited by the available load memory and work memory in the
CPU. There is no specific limit to the number of OB, FC, FB and DB blocks supported or to the size of a particular block;
the only limit is due to overall memory size.
2 For CPU models with relay outputs, you must install a digital signal board (SB) to use the pulse outputs. 8 SMs max.
SB, CB, BB expansion 1 max.
Communication module expansion 3 CMs max.
High-speed counters 6 total, see table Operation of the high-speed counter (Page 339)
Single phase: 3 at 100 kHz and 3 at 30 kHz clock rate,
Quadrature phase: 3 at 80 kHz and 3 at 20 kHz clock rate
Pulse outputs 2 4
Pulse catch inputs 14
Time delay / cyclic interrupts 4 total with 1 ms resolution
Edge interrupts 12 rising and 12 falling (14 and 14 with optional signal board)
Memory card SIMATIC Memory Card (optional)
Real time clock accuracy +/- 60 seconds/month
Real time clock retention time 20 days typ./12 days min. at 40°C (maintenance-free Super Capacitor) 16 from the program cycle or start up OB; 4 from the time delay
interrupt, time-of-day interrupt, cyclic interrupt, hardware interrupt,
time error interrupt, or diagnostic error interrupt OB Monitoring Status of 2 code blocks can be monitored simultaneously
Program cycle Multiple: OB 1, OB 200 to OB 65535
Startup Multiple: OB 100, OB 200 to OB 65535
Time-delay interrupts and
cyclic interrupts
41 (1 per event): OB 200 to OB 65535
Hardware interrupts (edges
and HSC)
50 (1 per event): OB 200 to OB 65535
Time error interrupts 1: OB 80
OBs
Diagnostic error interrupts 1: OB 82
Type IEC
Quantity Limited only by memory size
Timers
Storage Structure in DB, 16 bytes per timer
Type IEC
Quantity Limited only by memory size
Counters
Storage Structure in DB, size dependent upon count type
SInt, USInt: 3 bytes
Int, UInt: 6 bytes
DInt, UDInt: 12 bytes
1 Time-delay and cyclic interrupts use the same resources in the CPU. You can have only a total of 4 of these interrupts
(time-delay plus cyclic interrupts). You cannot have 4 time-delay interrupts and 4 cyclic interrupts.
Table A- 48 Communication
Technical data D8 for Open User Communication (active or passive): TSEND_C,
TRCV_C, TCON, TDISCON, TSEND, and TRCV
3 for server GET/PUT (CPU-to-CPU) S7 communication
8 for client GET/PUT (CPU-to-CPU) S7 communication
Data rates 10/100 Mb/s
Isolation (external signal to PLC logic) Transformer isolated, 1500 VAC, for short term event safety only
Cable type CAT5e shielded
1 The CPU provides dedicated HMI connections to support up to 3 HMI devices. (You can have up to 2 SIMATIC Comfort
panels.) The total number of HMI is affected by the types of HMI panels in your configuration. For example, you could
