 |
| Place of Origin: | Japan |
| Brand Name: | Tamagawa |
| Certification: | CE |
| Model Number: | TS5214N566 |
| Minimum Order Quantity: | 1pcs |
|---|---|
| Packaging Details: | carton |
| Delivery Time: | in stock |
| Payment Terms: | T/T, Western Union, MoneyGram |
| Supply Ability: | 100pcs/week |
| TAMAGAWA: | TAMAGAWA | TS5214N566: | TS5214N566 |
|---|---|---|---|
| Japan: | Japan | Material: | Iron |
| Color: | Black | Temperature: | 20-90 |
TS5214N566
Guang Zhou Lai Jie Electric Co.,LTD
Please contact with “Tommy” for the price
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| performed in a separate interrupt routine for easy state control. | you can use CTU, CTD, or CTUD counter instructions. |
| (Alternatively, all interrupt events can be processed in a single interrupt routine.) |
the events to be counted occur within the execution rate of the OB, |
| The high-speed counter (HSC) counts events that occur faster than the OB execution rate. | If the events occur faster than the OB execution rate, then use the HSC. The CTRL_HSC instruction allows your user program to programmatically change some of the HSC parameters. |
For example: You can use the HSC as an input for an incremental shaft encoder. The shaft
encoder provides a specified number of counts per revolution and a reset pulse that occurs
once per revolution. The clock(s) and the reset pulse from the shaft encoder provide the
inputs to the HSC.
The HSC is loaded with the first of several presets, and the outputs are activated for the time
period where the current count is less than the current preset. The HSC provides an interrupt
when the current count is equal to preset, when reset occurs, and also when there is a
direction change.
As each current-count-value-equals-preset-value interrupt event occurs, a new preset is
loaded and the next state for the outputs is set. When the reset interrupt event occurs, the
first preset and the first output states are set, and the cycle is repeated.
Since the interrupts occur at a much lower rate than the counting rate of the HSC, precise
control of high-speed operations can be implemented with relatively minor impact to the scan
cycle of the CPU. The method of interrupt attachment allows each load of a new preset to be
performed in a separate interrupt routine for easy state control. (Alternatively, all interrupt
events can be processed in a single interrupt routine.) The digital I/O points used by high-speed counter devices are assigned during device
configuration. When digital I/O point addresses are assigned to these devices, the values of
the assigned I/O point addresses cannot be modified by the force function in a watch table.
When you configure the CPU, you have the option to enable and configure each HSC. The
CPU automatically assigns the input addresses for each HSC according to its configuration.
(Some of the HSCs allow you to select whether to use either the on-board inputs of the CPU
or the inputs of an SB.)
NOTICE
As shown in the following tables, the default assignments for the optional signals for the
different HSCs overlap. For example, the optional external reset for HSC 1 uses the same
input as one of the inputs for HSC 2.
Always ensure that you have configured your HSCs so that any one input is not being used
by two HSCs.
